A frequency-divider having a variable frequency dividing factor (hereinafter variable frequency-divider) may be used as a pulse-swallow type prescaler in a PLL. An example of such variable frequency-dividers which have been conventionally used is shown in FIG. 1. The variable frequency-divider shown in FIG. 1 is in a semiconductor integrated circuit form. The variable frequency-divider of FIG. 1 has switchable frequency dividing factors of 64, 65, 128 and 130. A high frequency signal applied at an input terminal 10 is fed to a bias circuit 12 which provides a predetermined bias to the high frequency signal to ensure stable frequency-dividing operations in a .div.2 (divide-by-2) frequency-divider 19 and a .div.64(divide-by-64)/.div.65(divide-by-65) frequency-divider 18 which are described later. The biased high frequency signal from the circuit 12 is applied to an electronic switch 14. The electronic switch 14 has its movable contact 14a connected to a fixed contact 14b when a frequency dividing factor switching signal at a low (L) level is applied to a frequency dividing factor switching terminal 16. The movable contact 14a of the electronic switch 14 is connected to a fixed contact 14c when the frequency dividing factor switching signal applied to the terminal 16 is at a high (H) level. The contact 14b is connected to the input of the .div.64/.div.65 frequency-divider 18, whereas the fixed contact 14c is connected to the .div.2 frequency-divider 19, which has its output coupled to the .div.64/.div.65 frequency-divider 18. The .div.64/.div.65 frequency-divider 18 divides the frequency of a signal applied thereto by a factor of 64, when a mode switching signal at a low (L) level is applied to a mode switching terminal 20, whereas it performs divide-by-65 operation when the mode switching signal applied to the terminal 20 is at a high (H) level. Thus, when the low-level frequency dividing factor switching signal is applied to the frequency dividing factor switching terminal 16 and, at the same time, a low-level mode switching signal is applied to the mode switching terminal 20, the high frequency signal from the bias circuit 12 is applied through the electronic switch 14 to the .div.64/.div.65 frequency-divider 18, where it is frequency-divided by 64 and is developed at an output terminal 22. When the high-level mode switching signal is applied to the terminal 20 with low-level frequency dividing factor switching signal being applied to the terminal 16, the high frequency signal from the bias circuit 12 is applied through the switch 14 to the frequency-divider 18, where it is frequency-divided by 65. When the high-level frequency dividing factor switching signal is applied to the frequency dividing factor switching terminal 16 and the low-level mode switching signal is applied to the mode switching terminal 20, the high frequency signal from the bias circuit 12 is coupled through the electronic switch 14 to the .div.2 frequency-divider 19 where it is divided by a factor of 2. The output of the .div.2 frequency-divider 19 is applied to the .div.64/.div.65 frequency-divider 18 and is frequency-divided by 64. In other words, the high frequency signal from the bias circuit 12 is ultimately frequency-divided by 128. When the high-level mode switching signal is applied to the terminal 16 with the high-level frequency dividing factor switching signal being applied to the terminal 20, the high frequency signal from the bias circuit 12 is coupled through the electronic switch 14 to the .div.2 frequency-divider 19 where it is divided by 2. The thus frequency-divided signal is then coupled to the .div.64/.div.65 frequency-divider 18 and is frequency-divided by 65. In other words, the frequency of the high frequency signal is ultimately divided by 130.
The bias circuit 12 may include a differential amplifier 24 as shown in FIG. 2. The differential amplifier 24 includes two MESFET's 26a and 26b having their source connected together to a reference potential point 30 through a constant current source 28, having their drains connected through associated resistors 32a and 32b to a voltage supply line 34, and having their gates supplied with a bias voltage generated by a bias voltage generating circuit 38 through respective resistors 36a and 36b of the same resistance value. The bias voltage generating circuit 38 includes a series combination of a resistor 40, diodes 42, 43, 44 and 45 and a resistor 46 connected in the named order from the voltage supply line 34 to the reference potential point 30. A voltage developed at the junction between the diodes 43 and 44 is applied through the respective resistors 36a and 36b to the gates of MESFET's 26a and 26b as their bias voltage. The gate of the MESFET 26a is connected to the input terminal 10 to which the high frequency signal is applied through a capacitor 48 which is external to the frequency-divider circuit. The gate of the MESFET 26b is connected to an AC grounding terminal 50 which is grounded through a capacitor 52 external to the frequency-divider circuit. The drain of the MESFET 26b is connected to an output terminal 54 of the bias circuit 12, which terminal 54 is connected to the movable contact 14a of the electronic switch 14.
In the bias circuit 12, the predetermined bias voltage is applied to the gates of the MESFET's 26a and 26b from the bias voltage generating circuit 38, and equal drain currents flow from the drains to the sources of the respective MESFET's 26a and 26b. A constant voltage which is equal to the voltage on the voltage supply line 34 minus a voltage drop across the resistor 32b is developed at the output terminal 54. The gate of the MESFET 26b is AC conductively grounded through the capacitor 52, while the high frequency signal DC-blocked by the capacitor 48 is applied to the gate of the MESFET 26a. When the high frequency signal is positive, the drain current of the MESFET 26a increases and the drain current of the MESFET 26b decreases, so that the voltage drop across the resistor 32b is reduced, which results in an increase in the voltage at the terminal 54. On the other hand, when the high frequency signal is negative, the drain current of the MESFET 26a decreases and the drain current of the MESFET 26b increases. Then the voltage drop across the resistor 32b increases, so that the voltage at the output terminal 54 decreases. Thus, a high frequency signal varying about the above-stated constant voltage is developed at the output terminal.
The above-described frequency-divider circuit requires two terminals, namely, the frequency dividing factor switching terminal 16 and the mode switching terminal 20, for switching the frequency dividing factor. In addition, the bias circuit 12 requires the AC grounding terminal 50. Recently, it has been tried to reduce dimensions of semiconductor integrated circuit packages for such frequency-divider circuits, and, accordingly, it is desired to reduce the number of terminals as much as possible.
An object of the present invention is to provide a frequency dividing factor switchable frequency-divider circuit without terminals corresponding to the frequency dividing factor switching terminal 16 and the AC grounding terminal 50 of the bias circuit 12.